| User Papers |
| For Publication Only |
A Complete Verification Solution For Electro-Optical Devices Using Advanced VMM With RAL
Author(s): Zygmunt Pasturczyk, Paul Lungu [Nortel] |
|
Coverage Driven 1G-Ethernet Switch Verification with Reusable System Verilog Testbench Architecture
Author(s): Yijing Liu, Jenny Yun Guo, Matthew Becker [Freescale Semiconductor Inc.] |
|
Design Verification and the Designer: Bridging the Gap
Author(s): Theodore Humpal, Vishal Anand [Cisco Systems] |
|
ECO Hold Fixing using PrimeTime Distributed Multi-Scenario Analysis
Author(s): Hans Kumar [Broadcom Corp.] |
|
Evaluation of Synopsys's Clock Mesh Technology
Author(s): Troy N. Hicks [Hewlett-Packard Co.] |
|
Low Power Verification Methodology For DSP Core using SVTB
Author(s): Prashanth Cherukuri [Mediatek Wireless, Inc.] |
|
| MA1 - Design Planning and Timing Constraints |
Consistent Timing Constraints with PrimeTime
Author(s): Steve Golson [Trilobyte Systems] |
|
Floorplanning and Feasibility Analysis using ICC DP
Author(s): Kritti Pathak [Cisco Systems] |
|
| MA3 - Statistical Timing (SSTA) and Library Topics |
Composite Current Source: Model for Accurate Design Sign Off
Author(s): Purnabha Majumder [NVIDIA Corp.] |
|
Variation Aware Analysis using Primetime-VX
Author(s): Arvind N V, Ananth Somayaji, Abhishek Mishra, Ajoy Mandal, Hariprasad TT, Sandeep P, Nicolas Verkinderen, David Colin [Texas Instruments] |
|
| MA4 - Verification with VMM I |
Performance Verification of a Complex Bus Arbiter Using the VMM Performance Analyzer
Author(s): John Dickol, Kari O'Brien [MediaTek Wireless, Inc.] |
|
Using the New Features in VMM 1.1 for Multi-Stream Scenarios (Technical Committee Award Honorable Mention)
Author(s): Jason Sprott, Sumit Dhamanwala, JL Gray [Verilab], Clifford Cummings [Sunburst Design Inc.] |
|
| MB1 - SoC Design |
Hierarchical Design Implementation of a Complex SoC Using IC Compiler
Author(s): Young Koog, Harpreet Gill [Samsung Electronics], Tamiko Yoneyama [Synopsys Inc.] |
|
Improving Routing QoR, DFM and Runtime at 45 nm with Zroute Technology in IC Compiler
Author(s): Sunil Mehta, Vladimir Yutsis [Advanced Micro Devices], Linda Davidson, Frank Gover [Synopsys, Inc] |
|
| MB2 - Floorplan-Driven Synthesis Methodology |
The Chicken or The Egg: How to Get a Floorplan Before a Netlist
Author(s): Tume Römer [Ericsson AB] |
|
Using Design Compiler Topographical to Predict and Alleviate Congestion
Author(s): Dhivakaran Santhanam [Broadcom Corp.], Terry Lee [Synopsys, Inc.] |
|
| MB4 - Verification Reuse |
Bridging the Pre- and Post-Silicon Gap – a Post-Silicon Implementation of Vera for Switch ASIC Verification
Author(s): Kanad Roy [Broadcom, Corp.] |
|
Using Bind for Class-Based Testbench Reuse with Mixed-Language Designs (Technical Committee Award Honorable Mention)
Author(s): Doug Smith [Doulos] |
|
| MC4 - Verification |
Optimizing RTL Simulation Performance
Author(s): Scott Fields [NVIDIA Corp.] |
|
| MC7 - DFM |
PrimeYield-LCC-Based Litho-Checking Flow for 40nm IP Design
Author(s): Julia Luo, Tom Mahatdejkul, Swapna Putchala [ARM Inc.], Venkata Battaram, Ron Duncan, Susan Hu [Synopsys] |
|
| TA2 - Advanced Techniques for Modern Constraints |
Simplifying Constraints By Using More Generated Clocks
Author(s): Stuart Hecht [SJH Clear Consulting LLC] |
|
Trust Me, I'm Design Compiler! (Synthesis behaviour over varying slack)
Author(s): Philip Watson [ARM, Inc.] |
|
| TA3 - Parasitic Extraction and Custom Design |
Bitcell Extraction for SRAM Design Using Raphael-NXT
Author(s): Tom Mahatdejkul, Ling Chien, Swapna Patchula, Julia Luo, Ing Ming Chang [ARM, Inc.], Missing Venkata Battaram [Synopsys] |
|
SBPF Performance and Accuracy Evaluation (Best First-Time Presenter)
Author(s): Dan Prevedel [LSI Corp.] |
|
Using NanoTime to Analyze a Digital Memory Interface Logic
Author(s): Yun Mei Lim, Sudheesh Madhavan [Altera Corp.] |
|
| TA5 - HSIM Simulation |
Achieving Increased Simulation Productivity and Accuracy using Star-RCXT Parasitic Extraction and HSIM
Author(s): Shuxian Chen, Ai-Ling Yong, Kostas Pagiamtzis, Sudheesh Madhavan [Altera Corp.], Ravi Krishna Adusumalli [Synopsys] |
|
HSIM EM Analysis Integration Flow for Rambus High Speed FlexIO Interface Cell
Author(s): Jason Wei, Vijay Gadde, Ingrid Huang, Chanh Tran [Rambus Inc.], Sumit Vishwakarma [Synopsys] |
|
Power and Signal Reliability Using HSIMPlus
Author(s): Satinderjit Singh [ARM, Inc.] |
|
| TB1 -Design for Low Power |
A Predictable Approach to Reducing Clock-Tree Power using IC Compiler Low-Power CTS
Author(s): Hong Li, Narayanan Thondugulam, Santiago Fernandez-Gomez [Apple, Inc.], Shubharthi Datta [Synopsys] |
|
Automated Design Flow for Reducing Power in a High Performance Synthesizable Processor Core
Author(s): Arvind Parihar, Avishek Panigrahi [MIPS Technologies], Sharrone Smith [Synopsys] |
|
| TB4 - Verification Environments & Testbenches I |
Attacking Constraint Complexity in Verification IP Reuse
Author(s): Srinath Atluri, Ben Chen, Harish Krishnamoorthy [Cisco Systems, Inc.], Alex Wakefield, Balamurugan Veluchamy, Rebecca Lipon [Synopsys, Inc.] |
|
Smart Test Benches for Functional Verification of HDL Using MATLAB and Simulink with VCS Cosimulation and HDL Code Generation
Author(s): Eric Cigan, David Lidrbauch [The MathWorks] |
|
| TC2 - Low Power Design Methodologies |
Design for Power Gating - And What UPF Can, and Cannot, Do for You (Technical Committee Award)
Author(s): David Flynn [ARM, Inc.] |
|
Leakage Power Optimization : An Improved Synthesis Methodology
Author(s): Sandip Patra [Broadcom Corp.] |
|
| TC4 - Verification Environments & Testbenches II |
Implementing Layered Stimulus Models Using Implicit Encapsulation
Author(s): Neil Johnson [XtremeEDA Corp.] |
|
svunit: Bringing Agile Methods into Functional Verification
Author(s): Bryan Morris, Rob Saxe [XtremeEDA Corp.] |
|
| TC5 - Mixed-Signal Verification |
High Speed Memory Channel Module Verification Using XA Simulator
Author(s): Wen-Hung Lo [NVIDIA Corp.] |
|
Mixed Mode Verification of a High-Speed Transceiver with HSIM-VCS Co-Simulation
Author(s): Richard Saito, Ninh Ngo [Altera Corp.] |
|
| TC6 - AMS - Custom Designer |
Applied Common Interfacing Techniques Using OCP
Author(s): Erich Whitney [The MITRE Corp.] |
|
| WA1 - Aspects of Design Closure |
Achieving Antenna-Clean Design Using IC Compiler
Author(s): Ronald Kalim [Consultant], Johnie Au [Cypress Semiconductor] |
|
Power Rail Noise Minimization for EMC-Aware Design
Author(s): Patrice Joubert Doriol, Cristiano Forzan, Davide Villa, Davide Pandini, Renato Castellan, Daniele Cervini, Mario Rotigni, Giovanni Graziosi [STMicroelectronics], Giuseppe Contarino, Egidio Marzorati [Synopsys, Inc.] |
|
| WA2 - Advanced Test Techniques |
Breaking the Hierarchy Rules: An Advanced Hierarchical DFT Strategy for a 5 Million Flop Design
Author(s): Charles Njinda [Cisco Systems] |
|
Creating an Effective Physically-Aware Test: Data Mining and Test Volume Control
Author(s): Tom Olsen, Someshwar Gatty [Advanced Micro Devices] |
|
DFT in Line with the Design: Hierarchical Scan Compression
Author(s): Jianlin Yu, Santiago Fernandez-Gomez [Apple Inc.], Sandeep Kaushik, Aurelia De Colle [Synopsys, Inc.] |
|
| WA3 - FPGA |
Is SystemVerilog Useful for FPGA Design? ("Burn and Learn" versus "Learn and Burn")
Author(s): Stuart Sutherland [Sutherland HDL, Inc.] |
|
SoC Emulation in FPGA
Author(s): David Abada [Amicus Wireless Technology Inc.] |
|
| WA4 - Verification with VMM II |
Advanced VMM Transactor Development: Tips for Designing VIP You Wouldn't Mind Reusing (2nd Place - Best Paper)
Author(s): Kelly Larson [MediaTek Wireless, Inc.] |
|
An XML-Based Flow for RAL: The Experience of Automating Register Definition from Word Document Specification to VMM Testbench and DUT Implementation for a Home Networking Communication Chip
Author(s): Ritero Chi, Brian Etscheid, Ted Chang [Entropic Communications] |
|
| WA5 - ESP - CV |
Symbolic Simulation for Functional Verification of Embedded Memory Using ESP-CV
Author(s): Hongwei Zhu, Hemant Joshi, Umang Doshi, Rajaram Mouli [ARM, Inc.] |
|
Using ESP-CV for Dynamic Power Analysis of Custom Macros to Reduce Analysis Time and Improve Accuracy
Author(s): Stephen Bijansky, Bassam Mohd, Baker Mohammad [Qualcomm] |
|
| WB4 - Verification with Assertions |
If Chained Implications in Properties Weren't So Hard, They'd Be Easy (3rd Place - Best Paper)
Author(s): Don Mills [Microchip Technology] |
|
SystemVerilog Assertions - Design Tricks and SVA Bind Files (1st Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.] |