Industry leaders share insights into their increasingly complex and diverse verification challenges and how the R&D collaboration with Synopsys has yielded key technology addressing these challenges. More details about these breakthrough technologies as well as the obtained results are presented. Watch the video and learn how a panel of industry experts from MediaTek, Renesas, Freescale and Qualcomm were able to FastForward to advanced verification, and gain insights for your next project.
Kelly Larson, Sr. Technical Marketing Manager, Verification, MediaTek; Eiichi Fukita, EDA Platform Development, Renesas; Hillel Miller, SoC Verification and Emulation Manager, Freescale; Guy Levenbroun, Sr Engineer, Qualcomm

On June 7, 2011, Synopsys hosted an dinner event at DAC in San Diego, CA. Hear what industry leaders from AMD, Juniper Networks, nVidia, Qualcomm and Xilinx had to say about using HSPICE and CustomSim in some of today’s most challenging designs.
Dirk Robinson, Analog Design Engineer, AMD; Nikhil Jayakumar, Design Engineer, Global Circuits Team, Juniper Networks; Wen-Hung Lo, Senior Mixed-Signal Design Engineer, NVIDIA; Mohamed Abu-Rahma, Staff Engineer, Memory Circuit Design Team, Qualcomm; Min-Fang Ho, CAD Manager, IC CAD, Xilinx

On March 2, Synopsys hosted a special Verification Luncheon at DVCon 2011 in San Jose. Industry experts from Cavium Networks, Atheros, and AMD discussed complex real-world verification challenges and presented insights into best practices that help address them. This video provides a valuable opportunity to learn about new innovations in verification technology that enable improved performance and productivity.
Brian Hunter, Consulting Engineer, Cavium Networks; Michael Smith, Director IC Design, Atheros; Warren Stapleton, Senior Fellow, AMD

On January 31, 2011, Synopsys hosted its first HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about using HSPICE in some of today's most challenging designs.
Synopsys, Inc.

In this short but insightful interview, Warren Stapleton, Senior Fellow at AMD, discusses the unique challenges of modern day verification, including the growing complexity of today’s microprocessors designs and what this means for verification engineers.
Warren Stapleton, Senior Fellow, AMD; Michael Sanie, Director, Functional Verification Marketing, Synopsys

On June15, 2010, Synopsys hosted a special Verification Luncheon event at DAC in Anaheim, CA at which industry leaders from around the world discussed their success using the VCS functional verification solution to address a wide range of verification challenges. The proceedings were captured in this insightful video.
Ali Habibi Senior Formal Verification Engineer, NVIDIA; Maruthy Vedam Senior Staff Manager, Digital Design and Verification, Qualcomm; Hillel Miller Verification Methodology Manager, Freescale; Kazunari Horikawa Chief Specialist, Toshiba; Yuval Shay Staff Engineer, Mixed-Signal Verification.

In this session, Synopsys Fellow Janick Bergeron shares his vision on verification for the coming decade. Although many challenges and principals remain the same as they have for the last 20 years, the approaches to address them change due to the economics of IC design and development. By drawing upon past and current trends, future approaches to these verification challenges are highlighted and discussed.
Janick Bergeron, Fellow, Synopsys

First presented at DVCon 2010, this tutorial focuses on advanced verification techniques based on the latest VMM release. To help verification engineers get maximum benefit from VMM, this tutorial provides application-oriented information on key VMM features that will boost engineers' productivity and encourage re-use throughout a project's life-cycle and across projects.
Doug Smith, Doulos; Jon Michelson, Verification Central LLC; Faisal Haque, Qualcomm; Badri Gopalan, Synopsys; JL Gray, Verilab, Inc.; Ambar Sarkar, Paradigm Works, Inc.

Following the announcement that VCS was honored as a finalist in the 2010 DesignVision Awards, Swami Venkat, Sr. Director of Verification Marketing at Synopsys, discusses the latest innovations within Synopsys' industry-leading functional verification solution at Designcon 2010.
Synopsys

The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; Aaron Barker, Staff Engineer, Sun Microsystems; Eugene Chen, CAD Director, Alter; Sandeep Tare, Verification Methodology Engineer, Texas Instruments; Lyes Djama, Smart Power Design Flows Manager; Pierluigi Daglio, AMS Design & Verification Flows Manager, STMicroelectronics

Synopsys hosted a special VCS Verification Luncheon event at DAC in San Francisco, CA focused on the VCS functional verification solution. Verification R&D experts from leading companies discussed how they leverage VCS’s multicore performance, transaction-based verification, tight mixed-signal integration, comprehensive low power verification capabilities and proven methodologies to solve today’s toughest verification challenges.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; YC Wong, Director of IC Engineering, Broadcom; Shrenik Mehta, Sr. Director of Frontend Tools and OpenSPARC, Sun Microsystems; Faisal Haque, Director of Engineering, Qualcomm; and Amit Chowdhry, Member of Technical Staff, AMD

Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering

Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer

Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead

"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead