The Synopsys PrimeTime suite includes PrimeTime, PrimeTime SI, PrimeTime PX and PrimeTime VX. Anchored by the most trusted and advanced static timing signoff solution for gate-level designs, the PrimeTime suite offers comprehensive signal integrity analysis, statistical timing analysis and full chip power analysis in a single integrated environment.
- Key Benefits:
- HSPICE-Accurate Results Minimize Over-Design
- Integrated Design Environment Improves Productivity
- Fast Turn-around Time Speeds Analysis and Signoff
- High Capacity Approach Reduces Hardware Costs
- Complete Solution Ensures Comprehensive Signoff
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HyperScale
PrimeTime HyperScale technology extends PrimeTime static timing analysis to support designs beyond 500 million instances. It delivers between 5 and 10X better runtimes for the full chip timing analysis and 5 to 10X smaller memory footprint compared with classic flat analysis.
Multicore
As the trend in CPU performance improvement quickly shifts from raw computational speed to parallelism it is essential for EDA applications to take advantage of the new multicore architecture. PrimeTime delivers a comprehensive solution in this space that enables a broad set of designers to take full advantage of multicore performance on dedicated single boxes or across networked farms. The PrimeTime solution is unique in its flexibility to use distributed and threaded multicore processing in tandem to fully harness compute resources and accelerate timing analysis and signoff.
Advanced OCV
An accepted trend in the semiconductor industry, where process geometry is continuously shrinking, is the growing impact of variation in static timing analysis (STA). As on-chip-variation (OCV) effects continue to increase with shrinking geometry nodes, applying a flat global margin across the entire chip can lead to overdesign, reduced design performance, and longer timing closure cycles. The PrimeTime advanced OCV solution is a sophisticated technology that takes advantage of improved device-level variation modeling technique to provide the right balance between accuracy and performance.
What is the PrimeTime Special Interest Group (SIG)?
The Synopsys PrimeTime Special Interest Group (SIG) is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA). Increasing design size and complexity are putting tremendous pressure on design schedules. STA is a key technology used throughout the design process to accelerate design closure. As STA technology rapidly evolves, the PrimeTime SIG helps design teams stay abreast of the latest developments to help maximize their effectiveness and throughput.
PrimeTime SIG 2012 Events
PrimeTime SIG at SNUG India
Topic: Next-generation Hierarchical Timing Technology - Hyperscale
June 13, 2012, Dinner
PrimeTime SIG at DAC 2012
Topic: Next-generation Hierarchical Timing Technology - HyperScale
June 4, 2012, Dinner
PrimeTime SIG at DATE 2012
Topic: Gigascale Design Signoff with Advanced OCV, ECO Guidance and HyperScale
13, March 2012, Luncheon
PrimeTime SIG 2011 Events
PrimeTime SIG at SNUG Japan 2011
Topic: HyperScale Technology
September 7, 2011, Luncheon
PrimeTime SIG at SNUG India 2011
Topic: Next Generation ECO Guidance Technology
June 23, 2011, Reception
PrimeTime SIG at DAC 2011
Topic: Next Generation ECO Guidance Technology
June 6, 2011, Reception
PrimeTime SIG at EDS Fair 2011
Topic: Next Generation ECO Technology
January 28, 2011, Luncheon
PrimeTime SIG Events Archive
PrimeTime 2012 Webinar Series
On-Demand
Faster PrimeTime Signoff - Tips, Tricks and New Technology
Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.
Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure
Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
PrimeTime 2011 Webinar Series
On-Demand
Faster Clock Analysis and Debug
Analyze clock constraints sooner, identify problems quicker, and debug timing violations faster. Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Save Weeks Fixing ECOs with PrimeTime and IC Compiler
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer
This technical webinar will explain how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs.
Debug Timing Faster with PrimeTime Visualization Tools
Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.
Reducing Design Margins Using PrimeTime Advanced OCV - TSMC and User Views
Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC's views and support model for these new technologies.
PrimeTime 2010 Webinar Series
On-Demand
Performing Accurate Power Analysis on Low Power Designs Using PrimeTime PX
Learn how to analyze the effectiveness of low power techniques in your design, which modes of operation consume the most power, and how to deploy PrimeTime PX to optimize your design to meet low power requirements.
Faster ECO Fixing Flows with PrimeTime and IC Compiler
Learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively using Distributed Multi-Scenario Analysis for automatic set-up, hold and DRC fixing.
Reducing Design Margins Using PrimeTime Advanced OCV
Explains how Advanced On-Chip-Variation works in comparison to flat-derate OCV and statistical STA-based signoff technologies, and will contrast the cost of adoption and accuracy of these three methods.
Addressing Signal Integrity Noise in Low Power Design
Discusses the impact of low power design and the resulting requirements that drive the technologies in today's static timing analysis tools.