Comprehensive Solution Enables Rapid Ramp-up and Delivery of Advanced Custom IP

Synopsys and GLOBALFOUNDRIES Collaborate to Deliver Interoperable Process Design Kits (iPDKs) Synopsys Custom Design Solution Now Supported by GLOBALFOUNDRIES 65nm Process Technologies

Latest Release Includes Scalability, Convergence and Throughput for Large IC Implementation on Advanced Node Technology

Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities

Unified Cell-Based and Custom Implementation Solution Key to Accelerating Time-to-Market

Comprehensive Solution Delivers Golden Accuracy and Compact Libraries

Rapid3D Technology Solves Sub-45nm Extraction Accuracy and Runtime Challenges for Custom IC Design

HyperScale Technology Delivers 5 to 10X Boost in Performance and Capacity

PrimeTime 2009.12 Delivers New Threaded Multicore Performance to Address Signoff Bottleneck

Expands Custom Design Portfolio with Unified Extraction Solution

Speeds RTL-to-GDSII Turnaround Time Through Look-ahead Constraint Analysis

Synopsys, Inc., today introduced its In-Design Rail Analysis™ capability to accelerate design closure. Part of Synopsys' IC Compiler in-design ecosystem, In-Design Rail Analysis utilizes embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation.

Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that TSMC selected Synopsys' Galaxy™ Implementation Platform for their new Integrated Sign-Off Flow. The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys' Design Compiler® synthesis and IC Compiler physical implementation solutions, and the PrimeTime® sign-off and Star-RCXT™ extraction solutions - the industry yardsticks for IC design sign-off. The new flow is now available for 65-nanometer (nm) designs with planned extensions into other process technology nodes.

Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that Synopsys’ PrimeTime® PX solution, a key component of the Galaxy™ Implementation Platform and part of Synopsys’ Eclypse™ low power solution, has been successfully deployed at more than 175 semiconductor companies worldwide to perform highly accurate dynamic and leakage power analysis. Seamless integration within PrimeTime, the golden industry standard for timing and signal integrity signoff, has resulted in the selection of PrimeTime PX as the preferred power analysis solution at companies from all facets of the semiconductor industry.

Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced that MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multi-media solutions, has adopted Synopsys’ PrimeTime® SI solution for static timing analysis (STA) and signal integrity (SI) signoff. MediaTek selected the Synopsys PrimeTime SI solution to streamline the signoff flow for its new cutting-edge system-on-chip (SoC) designs targeted at 65-nanometer (nm) and below process technologies.

Synopsys, Inc. today announced that Renesas Technology Corp. has deployed Synopsys' PrimeTime® advanced on-chip variation (OCV) capability to help accelerate timing closure for 65-nanometer (nm) and below system-on-chip (SoC) designs. PrimeTime advanced OCV analysis is an efficient, easy-to-adopt solution that employs adaptive derating to accurately account for random and systematic process variations across an integrated circuit (IC).

Synopsys, Inc.. a world leader in software and IP for semiconductor design and manufacturing, today unveiled two key improvements to its PrimeTime® static timing analysis (STA) suite that deliver a dramatic boost to designer productivity. The latest release includes a flexible multicore processing technology that makes more effective use of both single-core and multicore CPUs across today's compute server farms, harnessing their compute potential. This release also introduces new runtime optimizations, allowing design engineers to run faster full timing and signal integrity (SI) analysis on their large designs early in the implementation process, thus reducing costly design closure iterations.

Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today announced that it has further expanded its long-standing relationship and technical collaboration with STMicroelectronics. The two companies have a long history of successful collaborations that have brought to market full-chip static timing analysis, formal equivalence checking and signal-integrity signoff tools.

Synopsys today announced the introduction of breakthrough Composite Current Source (CCS) base curve modeling technology that reduces digital cell library file size by up to 75 percent while improving application tool runtime and capacity. Starting at 65-nanometers (nm), and becoming critical at 45-nanometers, increased process variation and low power design flows, such as multi-voltage design, require more library corners as well as more complete and accurate power modeling views, causing library file size to increase ten-fold over the previous node. This is presenting a major storage, distribution and EDA tool efficiency challenge for the semiconductor industry.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that the Semiconductor Technology Academic Research Center (STARC) has incorporated Synopsys' PrimeTime® VX variation-aware, statistical timing signoff solution as part of its 65-nanometer (nm), Synopsys-based STARCAD-CEL methodology.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Toshiba Corporation has standardized on the open source Liberty™ Composite Current Source (CCS) modeling technology for its CMOS5/TC320C 65-nanometer (nm) production libraries.

Synopsys today announced that the Synopsys Star-RCXT™ parasitic extraction solution has been qualified and selected by more than 50 leading semiconductor companies to achieve silicon-accurate sign-off for System-on-Chip (SoC), ASIC, memory, custom digital and analog/mixed-signal 65-nanometer (nm) designs.