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Utilizing Design Compiler to Double Synthesis and P&R Productivity
See how new Design Compiler 2010 technologies double the productivity of synthesis and P&R by enabling RTL designers to perform floorplan exploration while still in synthesis.
Sandra Ma, Sr. Director, Corporate Application Engineer, Alak Ghosh, Staff Corporate Application Engineer Webinar
Jul 22, 2010 | | | New Enhancements for Debugging Inconclusive and Non-Equivalent Verifications in Formality
This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality.
Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.
Mitch Milner, R&D Group Director of Formal Verification
Jun 24, 2010 | | | Static Verification Throughout the Low Power Design Flow
Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010 | | | Reducing the Cost of Pin-Limited Test Using DFTMAX Compression
Designers are increasingly adopting design-for-test methodologies that limit the number of pins allocated for manufacturing test. During this technical webinar, we will examine what is driving this trend and how you can use new capability in DFTMAX compression to reduce the cost of pin-limited test for your designs.
Adam Cron, Principal Engineer, Synopsys; Girish Patankar, Senior R&D Manager, Synopsys
Apr 21, 2010 | | | Design Compiler 2010: Double the Productivity of Synthesis and Place & Route
Learn about a new capability in Design Compiler that allows RTL designers to perform floorplan exploration from within the synthesis environment to efficiently achieve an optimal floorplan. Hear about Design Compiler’s new scalable infrastructure tuned for multicore processors yielding 2X faster synthesis runtimes on quad-core compute servers.
Janet Olson, Sr. Director, R&D, Synopsys; Sandra Ma, Sr. Director, Corporate Applications Engineer, Synopsys
Apr 20, 2010 | | | Boosting Yield and Increasing Quality with Power-Aware Test and Small Delay Defect Testing
Join us for an in-depth technical webinar focused on new capabilities in DFTMAX™ compression and TetraMAX® ATPG that efficiently manage tester power and screen hard-to-detect defects.
Arif Samad, Group Director R&D, Synopsys; Adam Cron, Principal Engineer for Test Automation, Synopsys
Aug 05, 2009 | | | Successful Equivalence Checking of Highly Optimized DC Ultra Designs
Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.
Mitchell Mliner, Synopsys
Apr 21, 2009 | | | Accelerate your design closure with DC Ultra
Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma, Synopsys; Janet Olson, Synopsys
Apr 21, 2009 | | |
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