In this webinar, you will be introduced to the Altera SoC FPGA for the Altera Cyclone V and Arria V SoC FPGA devices and its associated Virtual Target.
Stephen Lim, Product Marketing Manager, Altera; Marc Serughetti, Product Marketing Director, Synopsys
Apr 19, 2012

In this webinar, Continental will describe the importance of fault-tolerance mechanism and fault-injection techniques for Automotive Tier-1's using as an example an Electronic Stability Control system. HW fault-tolerance mechanisms available in "state-of-the-art" Micro-Controller Units will be introduced by Freescale. Synopsys will disclose how Virtual Prototyping technology can be used to overcome many of the limitations of existing fault-injection techniques. Realistic fault-injection scenarios will be shown using a Freescale lock-step dual core virtual MCU model.
Victor Reyes, Technical Marketing Manager, Synopsys; Manfred Thanner, Technical Staff Systems Engineer, Freescale Semiconductor
Sep 19, 2011

This webinar introduces a solution to the challenges that software developers face when bringing up or optimizing system power management.
Achim Nohl, Solution Architect, Synopsys
Jun 30, 2011

Can hardware and software be developed for SoCs independently, or are the two so tightly coupled they must be developed concurrently? Can modeling the "system" wait until actual silicon is available, or must it be done with better tools at the architecture stage before the SoC is created?
Synopsys, Mentor and Cadence
Oct 14, 2009

Predicting the future is a hazardous endeavor, but tracking trends can at least provide a glimpse of what is to come. A key trend in embedded systems is the increasing need for reduced power consumption, which is driven by demand for portable devices, higher energy costs and environmental pressures. The role of embedded software and real time operating systems in delivering power reductions on target embedded hardware is not obvious. In this session the key factors will be reviewed in detail.
Synopsys and Mentor Graphics
Jul 15, 2009

The challenge for EDA tool vendors in attacking electronic system level (ESL) design can be simply stated - provide the tools and methodologies that let system-on-chip (SoC) designers use abstract, system-level models to create implementation-ready (RTL) descriptions of their desired hardware. The challenge for designers, on the other hand, is in negotiating their through the variety of point tools offered by many vendors who've staked out a position in the ESL tool market. This webinar will place the sponsors current offerings in perspective and provide some insight into ESL adoption.
Synopsys, Cadence, Mentor Graphics and CoWare
Jul 06, 2009

For the programmer and system developer, this E-Cast offers a real-time look at multicore technology from the perspectives of a virtual platform vendor, a processor vendor, an ESL solution provider and an operating system and hypervisor software vendor.
Synopsys, CoFluent Design, MIPS Technologies and Wind River
Mar 12, 2009

An Example-based Approach to Transaction-level Modeling and the New World of Model Interoperability. A set of six tutorials presented at the Design and Verification Conference (DVCon) 2009. Please make sure you see tutorial number 6, titled Applying TLM 2.0 to Legacy Platforms.
Presenter is Frank Schirrmeister and others
Feb 23, 2009

Today's multi-mode, multi-application systems place demanding performance requirements on the global resources of the SoC. Estimating bandwidth with spreadsheets is not viable, when dynamic workloads make it impossible to predict performance across all configurations of the interconnect and memory subsystem.
Tim Kogel
Feb 15, 2009

Are your SoC and embedded design projects increasingly dominated by software development schedules? Join Amelia Dalton as she talks with Frank Schirrmeister of Synopsys about ways to improve software development productivity using virtual platforms.
Synopsys