Seminar Overview:
Increases in the size and complexity of today’s semiconductor and electronic designs have intensified the verification challenges, thereby requiring advanced technologies and methodologies to ensure the highest design quality. This free seminar provides a forum to learn more about improving the productivity of the entire project team by addressing challenges for both hardware and software design flows with Synopsys’ best-in-class portfolio of system-level, functional and analog verification tools, models and services.

In addition to presentations and demonstrations of the latest advances of the Synopsys System-to-Silicon Verification Solution, you’ll hear customer success stories illustrating how design teams worldwide are successfully using this solution to meet their most complex design and verification challenges.

Who Should Attend:
Managers and engineers who are involved in the design, verification and validation of semiconductors, electronic systems and embedded software.

Seminar Topics:

• High-Level Block Design: Rapidly create differentiated IP blocks through Algorithm Design, High-Level Synthesis, and Custom Processor Development
• Architecture Design: Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost
• Virtual Prototyping: Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
• Functional Verification: Find design bugs faster and achieve rapid convergence coverage to significantly improve quality for the most complex designs
• FPGA-based prototyping: Accelerate the creation of your ASIC prototype with high-speed hardware prototyping systems including a comprehensive software flow

Primary Seminar Agenda (agenda may vary in some locations)

S2S Verification Solution Schedule:

Customer Keynote Speakers

Sudhakar Kale
Director, Fusion SoCs and GNBs, AMD

Sudhakar has over 20 years of extensive experience in the semiconductor industry, focusing on both front-end and back-end processes. This includes DSP, X86processors, Itanium server designs, CPU/GPU verification, testbench development, multimedia verification, front-end methodology development, power management, data path synthesis, placement algorithms, EM/Self-heat solutions, adaptive power management techniques, RC extraction and minimization techniques, memory compilers development, post-si bring-up and validation. Previous to AMD, he has worked at Texas Instruments, Synopsys, and Intel. Sudhakar has two patents and nine published papers to his credit. He holds a BE from JNTU, Kakinada, ME from the University of Hyderabad, and an MBA from Colorado State University.

Sudhakar will be a keynote speaker at the Synopsys S2S Verification Seminar in Hyderabad, on May 3, 2011.

Uday Joshi
Director of Engineering, Design and Verification, Qualcomm

Uday’s career spans many years, having worked at multiple startups (Paxonet, Acron, Azanda, Nexgen) and with Intel and Qualcomm. He has a wealth of experience in the end-to-end design cycle of VLSIs, FPGAs and software. He has engineered and managed multiple design and verification of various IPs, SoCs, Processors and ASICs, predominantly in the areas of networking and graphics. He currently holds six U.S. Patents. Uday graduated with a BE and ME from VJTI, Mumbai.

Uday will be a keynote speaker at the Synopsys S2S Verification Seminar in Bangalore, on May 5, 2011.

Kaushik Saha, PhD
Principal Member Technical Staff,
Advanced Systems Technologies, STMicroelectronics

Dr. Kaushik Saha joined STMicroelectronics, Ltd. (previously SGS-Thomson Microelectronics, Ltd.) in 1996, after graduating with a BE, ME and PhD from the Indian Institute of Technology, Delhi. He joined the organization as a designer of semiconductor memories in the Memory Products Group. Subsequently, he worked for the Applications Lab of the company and was involved in the design of consumer electronics systems of devices designed and fabricated by the company. He is currently involved in the research and development of next-generation devices and systems. Dr. Saha’s research interests are in the areas of Advanced Processor Architectures and Parallel Algorithms & Architectures for Digital Signal Processing Applications, in which he holds various patents and publications. He is also associated with the Indian Institute of Technology, Delhi, in the capacity of Adjunct Faculty.

Dr. Saha will be a keynote speaker at the Synopsys S2S Verification Seminar in Noida, May 9, 2011.