Join our
FREE DesignWare® IP Seminar to learn how the latest features in Synopsys' high-quality DesignWare IP portfolio can help you reduce risk and speed time-to-market for your system-on-chip (SoC) designs.
Daniel Hotel
Tuesday, February 16, 2010
8:30 to 14:00
60 Ramot Yam Street
Herzelia, IsraelREGISTER NOW Topics Include:
Live demonstrations featuring: - SuperSpeed USB 3.0: 10x the data transfer of Hi-Speed USB
- HDMI: The heightened viewing experience with higher video resolution
- SATA: Experience real data transfer performance with SATA 6Gb/s
- PCI Express® 2.0: Controller, PHY and verification IP solution demo
- Audio IP: A live performance of DesignWare Hi-Fi Audio IP
Who Should Attend?Design and verification engineers, managers, and architects developing SoCs
Prize DrawingAll attendees will be instantly qualified to win one of the latest high-tech products on the market!
Registration is FREEClick here to register for the DesignWare IP Seminar
Agenda| 8:30 - 9:00 | Registration, Breakfast, Demonstrations | | 9:00 - 9:30 | Introduction Keynote: How Semiconductor Trends are Influencing the Use of IP | | 9:30 - 10:30 | Analog IP for Wireless and Multimedia Applications | | 10:30 - 10:45 | Break and Demonstrations | | 10:45 - 11:45 | System-Level Considerations for Achieving High-Speed DDR Interfaces up to 2133 Mbps | | 11:45 - 12:45 | New Design Techniques Enabling Analog/Mixed-Signal IP Integration in the 65-28-nm SoC Era | | 12:45 - 13:00 | Prize Drawing | | 13:00 - 14:30 | Lunch and Demonstrations |
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- Keynote: How Semiconductor Trends are Influencing the Use of IP
John Koeter, Vice President of Marketing for the Solutions Group at Synopsys, discusses the latest trends in the semiconductor industry and how they are influencing the use of third-party IP in complex SoCs. Companies are increasingly outsourcing IP in order to focus engineering efforts on their core competencies and product differentiation. Mr. Koeter will discuss how Synopsys is delivering high-quality interface and analog IP solutions that enable designers to integrate the latest functionality into their SoC while reducing risk and improving time-to-market.
- Analog IP Portfolio for Wireless and Multimedia Applications
Today's consumer electronics are providing access to and communication of large amounts of digital content. The transferring and storing of this content requires a number of high-speed standard digital interfaces, some of which require handling of analog signals with high dynamic range, such as audio and video. While wired, high-speed digital connectivity allows simple connections between different multimedia devices (e.g., HDMI, etc.), wireless links are becoming more prominent among today's "digital living rooms" and enterprise infrastructures. While these bring added flexibility and comfort, such wireless links require considerably complex handling of analog signals. This session provides an overview of the DesignWare® Analog IP Portfolio and how it enables audio, video and wireless communications interfaces for many devices in the market.
- System-Level Considerations for Achieving High Speed DDR Interfaces up to 2133 Mbps
JEDEC's DDR3 roadmap is being extended to support devices up to 2133 Mbps which will challenge robust operation in embedded systems. In order to close timing, designers will have to scrutinize their system-level timing budgets. For successful timing closure, signaling effects once considered secondary will now claim a significant portion of the memory system timing budgets. Signaling effects such as synchronously switching outputs, skew, modal dispersion and crosstalk now must be addressed with care to ensure the signal integrity of the entire memory system. This presentation will highlight the many challenges in DDR systems and outline the features of Synopsys DDR IP solutions to enable reliable high-speed DDR memory systems.
- New Design Techniques Enabling Analog/Mixed-Signal IP Integration in the 65 nm to 28 nm SoC Era
This presentation will focus on the emerging techniques that enable the design and integration of high-speed interfaces used on next-generation system-on-chips (SoCs). Designers now expect that the complete interface functions correctly on the SoC, regardless of the speed or the manufacturing variations in the technology. In many cases IP development is done without knowing in detail the SoC environment. Using USB and DDR examples, the multi-gigabit per second physical and digital controller integration, complexity of the protocol and variations in these leading edge technologies (transistor miss-match, hot carrier effects, I/O voltage) will be described from the IP development and integration perspectives.
How to Register Registration is free.
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