Issue 1 - 2012
Partner Highlight
Combining Tools and Technology for 20nm Gigascale ICs
Synopsys and Samsung explain the alignment of their respective technology roadmaps to address the emerging challenges for next-generation 20nm-based design.
Technology Update
Discovery: A New Generation of Verification IP
Verification intellectual property (IP) has shown its worth over recent years as a vital component in enhancing SoC verification productivity. Learn more about how Synopsys Discovery VIP can help designers accelerate and simplify verification of the most complex SoC designs.
A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather than by Revolution
Learn about technology trends, timeline, and the impact on EDA, as the industry moves closer to making 3D-IC design mainstream.
Constraint Analysis Makes For More Predictable Tapeout
Learn how design managers can save weeks of engineering time without disrupting design flows by using look-ahead timing constraint analysis to reduce the risk of unexpected delays.
The Fast Track to 3D-IC Testing
Learn about a design-for-3D test architecture and implementation flow developed to enable cost-effective, high-volume production.
Executive Spotlight
Industry Initiatives: Discovery Verification IP
George Zafiropoulos, Vice President, Synopsys Solutions Marketing, talked to Synopsys Insight about the company’s most recent verification initiative: Discovery VIP.
Synopsys Innovation Update
Latest News on Product Updates, Technologies, Services and Solutions
Learn about some of the recent innovations Synopsys is providing its customers.
Standards Column
Do Standards Matter to Users? You Bet!
Learn how standards benefit customers and why they should actively participate in the development of standards to help move their innovative designs from concept to silicon and then into a system in the most efficient manner.
Issue 4 - 2011
Technology Update
Build Low-Power, High-Performance Mobile SoCs with Complete MIPI Solutions
Consumers expect more and more from mobile electronics. Discover how the MIPI Alliance protocols and interfaces are addressing market needs and how MIPI IP can help you build your SoCs quickly and easily.
Reducing Power with Advanced Synthesis
Learn how the new advanced power optimization techniques in Power Compiler™ enable design teams to significantly reduce dynamic and leakage power in their designs.
Achieving Faster Hierarchical Design Throughput
As SoC designs continue to get larger and more complex, schedules for physical designs are staying the same or getting even shorter. Understand how the new On-Demand Loading technology within Synopsys’ IC Compiler helps engineering teams produce an accurate floorplan in less time.
Next-Generation Low-Power Data Converters for High-Performance Communication Applications
Explore how the next generation DesignWare® Data Converter architecture uses digital calibration to deliver higher performance with up to 50% power and area savings compared to previous generations of data converters.
High-Performance Analog Simulation with Multicore CPUs
Analog and mixed-signal design teams are more dependent on verification than ever before. Learn how to extract more performance out of the HSPICE® circuit simulation environments with HSPICE Precision Parallel technology, even when performing transient noise analysis.
The Next Major Shift in Verification is SoC Verification
Discover why it's time for the next EDA revolution to bring about an order-of-magnitude increase in verification productivity.
Executive Spotlight
An Insider Look into the EDA Industry’s Largest Technical Conference: SNUG
Insight talked to Ken Nelsen, SNUG’s Executive Sponsor and Synopsys’ Vice President of Applications Consulting, for a look into SNUG: Your Global Design Community Focused on Innovation.
Synopsys Innovation Update
Latest News on Product Updates, Technologies, Services and Solutions
Find out about some of the recent innovations Synopsys is providing its customers.
Standards Column
Four Reasons Why Synopsys Supports Industry Standards
Learn more about how standards are directly linked to innovation and how standards-based tools help designs move from concept to silicon and then into a system (an end product) in the most efficient manner.
Issue 3 - 2011
Partner Highlight
Interoperable Process Design Kits (iPDKs) Gain Momentum
Learn about the latest developments and the benefits iPDKs provide to foundries and design teams.
Technology Update
Signoff-Driven ECO Guidance for Faster Timing Closure
Learn how the Synopsys PrimeTime static timing analysis solution helps design teams to efficiently deal with timing signoff ECOs.
Optimized Processor Cores – What You Need to Know
Learn how to evaluate processor core benchmark numbers and understand the trade-offs when choosing a processor core.
TLMCentral: The Industry-Wide Web Portal for Transaction-Level Modeling
Learn how the new TLMCentral web portal provides easy access to transaction-level models to accelerate adoption of Virtual Prototypes.
In-Design Physical Verification: Automatic DRC Repair
Learn how design teams can use automatic DRC repair, a feature of in-design physical verification, to automatically detect, repair and revalidate signoff DRC violations.
Accelerating Virtual Prototype Development
Learn how Virtualizer helps designers to create virtual prototypes and developers to use them.
Estimating Circuit Lifetime
Learn how design teams can cost-effectively estimate the lifetime of circuits.
Overcoming Cost and Complexity in Verification
Learn how to quickly verify your designs and easily improve the quality of the most complex designs, and achieve first-pass silicon success.
Executive Spotlight
Industry Initiatives: Enabling Virtual Prototyping
Synopsys Insight talked to John Koeter, Synopsys' Vice President of Marketing for the Solutions Group, to get executive insight into one of the company's latest industry initiatives: TLMCentral.
Synopsys Innovation Update
Latest News on Product Updates, Technologies, Services and Solutions
Learn more about the recent innovations Synopsys is providing its customers.
Standards Column
Setting Standards: Will the Best Technology Win?
Learn what to look out for when getting involved in a new standard and understand how the structure and process followed by a committee can influence the outcome of a project.
Issue 2 - 2011
Synopsys and TSMC Go Virtual with 28nm Reference Flow
Learn about the new reference flow for TSMC’s 28-nanometer (nm) process technology. With the introduction of virtual prototyping, project teams can develop software and tune the hardware architecture before silicon is available.
Faster Simulation Without More Hardware
How can design and verification engineers improve the simulation performance of modern high-performance CPU cores? AMD’s Neil McKenzie and Synopsys’ Vijay Akkaraju look at various techniques.
Virtual Prototyping for Software Developers
Virtual prototyping is becoming increasingly important to embedded software developers, engineers, managers and marketing teams. Learn what virtual prototyping is and how those affected by growing hardware-software complexity can use it to produce better software and systems, faster.
Accelerate Design by Exploring Early RTL and Constraints
RTL development involves lengthy iterations of synthesis and refinements to the RTL and constraints, a major risk to project schedules. Learn how DC Explorer helps designers reduce the time it takes to produce a better starting point for RTL synthesis.
DesignWare® IP: Product Updates and Customer Successes
Synopsys enables designers to reduce integration risk and accelerate time-to-market by providing high-quality, silicon-proven interface IP, analog IP, embedded memories, logic libraries, processor cores and SoC infrastructure IP. As the leading provider of semiconductor IP solutions for SoC designs, Synopsys is continuously enhancing its DesignWare IP portfolio. Learn more about the latest product updates and customer successes.
EDA in the Clouds: Myth Busting
Synopsys’ David Hsu dispels a few myths and brings us up-to-date with the latest in the Synopsys cloud story.
The Standards Column: DAC Meeting Highlights Standards Progress
The world of semiconductor standards and interoperability is constantly evolving. Read about the latest progress update that was presented at the annual Interoperability Breakfast held during the Design Automation Conference (DAC).
Biggest SNUG Ever Kicks Off the 2011 Global SNUG Program
Have you made it to a Synopsys Users Group (SNUG) conference yet this year? We report the highlights from the kick off of the 2011 program at SNUG San Jose – the benchmark for EDA user conferences, and look forward to meeting with customers at the other 13 SNUGs that will be held around the world during the rest of the year.
DAC 2011 in Review
Read about the Synopsys’ DAC 2011 program highlights and key announcements including the latest agreement with ARM and the winner of the eleventh annual Tenzing Norgay Interoperability Achievement Award.
Recent and Upcoming Speaking Events
Synopsys executives are regularly invited to speak on a broad range of topics at key industry events around the world. See our summary of recent and upcoming speaking events that feature Synopsys speakers with links for access to additional information.
Introducing the FPGA-based Prototyping Methodology Manual
The FPMM is the first reference book to collect and present comprehensive best practice advice on the use of FPGAs for prototyping.
Expanding Synthesis-based Test for Higher QoR and Lower Cost
Advanced test technology is enabling designers to achieve optimal quality of results (QoR) and eliminate time-consuming iterations between design and test.
Optimizing Multicore System Performance
System architects can now define and analyze multicore systems. Multicore Optimization technology, part of Platform Architect, enables design teams to more accurately predict system performance using SystemC months before software is available.