| Time | Description |
| 7:30-9:00 | Registration and Breakfast |
| 9:00-10:30 | Welcome and Introduction
KEYNOTE ADDRESS: John Chilton - Senior Vice President, Marketing & Strategic Development, Synopsys Inc. |
| 10:30-10:45 | Break |
| | Front End Implementation | Verification | Custom Design & AMS Verification | Back End Implementation |
| 10:45-12:15 | MA1 User
System Verilog & Improving Coverage with DFT Compiler | MA2 User
SystemVerilog & Low Power Verification | MA3 Tutorial
Synopsys Custom Design Solution | MA4 User
Tips and Tricks for Leakage and Useful Skew |
| 12:15-1:15 | Lunch |
| 1:15-2:45 | MB1 User and Tutorial
AOCV Analysis with PrimeTime & Low Power with DesignWare minPower | MB2 Tutorial and User-torial
Advanced Verification Technologies | MB3 User and Tutorial
Circuit Checks and Reliability Analysis | MB4 User
Advanced Routing Techniques for DRC and ECO |
| 2:45-3:00 | Break |
| 3:00-4:30 | MC1 Tutorial
Latest Design Compiler Technologies | MC2 Tutorial and Panel
X Propogation in GLS & Verification Challenges | MC3 Tutorial
Solving the Latest Parasitic Extraction Challenges with StarRC | MC4 User and Tutorial
Block Feasibility with ICC and 3D-IC |
| 4:30-6:30 | Awards Presentation & Synopsys Mixer Night |