| Time | Description |
| 8:00-9:00 | Registration and Breakfast |
| 9:00-10:30 | WELCOME: Jay Wasserman, Analog Devices Inc. and SNUG Boston Technical Chair
KEYNOTE ADDRESS: Dr. Aart de Geus - CEO & Chairman of the Board, Synopsys, Inc. |
| 10:30-11:00 | Break |
| | IC Verification | FPGA | IC Design: Synthesis, Power, Flows & Formality | IC Design: Physical Implementation & Static Timing | IC Design: Physical Verification & Test | AMS & Verification |
| 11:00-12:30 | TA1 User and Tutorial
Integrating UVM-SystemVerilog within a C/C++ environment | TA2 Tutorial
Prototyping | TA3 Tutorial and User
DC Explorer and DC Physical Guidance | TA4 User
Power Recovery and Power Rails | TA5 Tutorial
StarRC and ICV | TA6 User and Tutorial
HSPICE |
| 12:30-1:30 | Lunch |
| 1:30-3:30 | TB1 User
Advanced VCS Verification Topics | TB2 Tutorial
FPGA Synthesis | TB3 User and Tutorial
Low Power | TB4 Tutorial and User
ICC New Features and Custom Designer Interface | TB5 User and Tutorial
Advanced Test Techniques | TB6 Tutorial and User
Discovery AMS, XA and Custom Designer |
| 3:30-3:45 | Break |
| 3:45-5:15 | TC1 Tutorials
Reusable Verification IP | TC2 Tutorial
FPGA Synthesis | TC3 User-torial and Tutorial
Lynx and Formality | TC4 User and Vision
PrimeTime Advanced Technology | TC5 Tutorial
Test | TC6 Tutorial
Custom Design |
| 5:00-7:00 | Designer Community Expo and Awards Presentation |