IEEE Standard 1800™-2005 SystemVerilog is the industry's unified hardware description and verification language (HDVL) standard. SystemVerilog is a significant evolution of the traditional Verilog hardware description language. Its use dramatically improves productivity in the development of large-gate-count, IP-based, and bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flows, with powerful links to the system-level design flow. SystemVerilog has been adopted by hundreds of semiconductor design companies and is supported by more than 75 EDA, IP, and training solutions providers worldwide.

Synopsys’ support for SystemVerilog
As a pioneer in the development of the SystemVerilog standard, Synopsys provides comprehensive support for SystemVerilog throughout its solutions, platforms, and design and verification tools.