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Conference at a Glance

Conference at a Glance

SNUG Silicon Valley | March 26-28, 2012

Monday, March 26, 2012
Tuesday, March 27, 2012
Wednesday, March 28, 2012 - Including IP Summit at SNUG

Monday, March 26, 2012

Time	Description
7:30-9:00	Registration
9:00-10:30	WELCOME: John Busco - SNUG Silicon Valley Technical Chair, NVIDIA KEYNOTE ADDRESS: Dr. Aart de Geus - CEO & Chairman of the Board Synopsys, Inc.
10:30-11:00	Break
	IC Design - Implementation A	IC Design - Implementation B	IC Verification	AMS Verification	FPGA	IC Design - Signoff
11:00-12:30	MA1 Tutorial: Galaxy RTL: Design Compiler Family Update Synopsys, Inc.	MA2 Tutorial: IC Compiler Custom Co-Design Synopsys, Inc.	MA3 User: UVM Factories & USB 3.0 Verification The OVM /UVM Factory & Factory Overrides - How They Work - Why They Are Important Sunburst Design ------ Integrating DesignWare USB3.0 Device Controller In a UVM-Based Testbench Paradigm Works	MA4 User: Advanced Analysis w/ HSPICE & CustomSim-VCS Statistical Margin Sensitivity to RNG option for Monte Carlo Simulations w/ HSPICE ARM ------ UVM based Random Verification in Analog & Mixed Signal Designs for Faster Coverage Closure AMD	MA5 Tutorial: Consider- ations in Using FPGAs as System Elements Synopsys, Inc.	MA6 User & Tutorial: Signoff-Driven Design Closure PrimeTime DMSA ECO Fix: a Case Study Cypress Semiconductor ------ ECO Timing Closure: Fast & Flexible Multi-Scenario DRC Fixing Synopsys, Inc.
12:30-1:45	General Lunch in Hall D
12:30-1:45	Lunch and Learn in Mission City Ballroom Leading Semiconductor Companies Discuss Move from In-Design to Signoff with IC Validator
	IC Design - Implementation A	IC Design - Implementation B	IC Verification	AMS Verification	FPGA	IC Design - Signoff	IC Design - Custom Design
1:45-3:15	MB1 User: Design Correlation Improving Virtual Route Correlation on Advanced Process Nodes Intel, Corp. ------ The Impact of Correlation on Design Quality, Design Closure Loops, & Design Turn Around Time Intel, Corp.	MB2 Tutorial: Accelerating Manufacturing Closure at 28nm & below w/ IC Validator & In-Design Technology Synopsys, Inc.	MB3 User: Minimizing RTL-to-Netlist Simulations Mismatches VCS X-Prop: An Alternative to Gate Level Simulation ------ Simulation/ Synthesis Mismatches Again? Microchip Technology	MB4 User & Tutorial: Testability for Custom Logic & 28nm Cell Character Challenges Enabling DFT Logic & Timing Verification in Mixed-Signal Designs w/ XA & VCS Cosim Rambus ------ Standard Cell Library Character Flow using Liberty-NCX & HSPICE Synopsys, Inc.	MB5 Tutorial: Design Reliability Challenges for 28nm & Beyond Synopsys, Inc.	MB6 Vision: Signoff for Increasingly Complex Designs Synopsys, Inc. ------ Q&A Panel Synopsys, Inc.	MB7 Workshop: Custom Designer Synopsys, Inc.
3:15-3:45	Break
	IC Design - Implementation A	IC Design - Implementation B	IC Verification	AMS Verification	FPGA	IC Design - Signoff	System-Level Design
3:45-5:15	MC1 Tutorial: Design Correlation Flipchip Package Design Intelligent & Automated Layer-Aware Pre-Route Optimization for Improved Post-Route Correlation for Advanced Technology Nodes Synopsys, Inc. ------ A Chip-Package Design Flow Using Zuken & Synopsys Tools Zuken, Synopsys, Inc.	MC2 User & Tutorial: IC Validator Enabling DRC+ Pattern-based Physical Verification w/ IC Compiler & IC Validator GLOBALFOUNDRIES ------ Optimizing Design Fill at 28nm & below using In-Design Physical Verification w/ IC Validator AMD	MC3 User: Enhancing Self-Checking Testbenches Snooping to Enhance Verification in a VMM Environment LSI Corp. ------ A Unified Self-Check Infrastructure Charles Stark Draper Labs	MC4 Tutorial: How to Get the Most from Your Circuit Simulation Synopsys, Inc.	MC5 User: FPGA Design Design & FPGA Implmentation of FIR Filters using Microprogram Control Unit King Abdulaziz City for Science & Technology	MC6 Tutorial: Static Timing Technology Performance & Productivity Improvements in PrimeTime 2011 Release Synopsys, Inc. ------ Galaxy Constraints Analyzer: Comparing Multiple SDC Constraints Files Synopsys, Inc.	MC7 User & Tutorial: UVM for ESL & HLS for Multi-Rate Comm. Designs Does UVM Make Sense for ESL? Doulos Inc. ------ Using High-Level Synthesis to Streamline ASIC Multi-Rate Comm. Design Synopsys, Inc.
4:00-8:00	Designer Community Expo

Tuesday, March 27, 2012

Time	Description
7:30-9:00	Registration
9:00-10:00	Keynote Address: John Cornish, Executive VP - ARM
10:00-10:30	Break
	IC Design - Implementation A	IC Design - Implementation B	IC Verification		FPGA	IC Design - Signoff	System-Level Design
10:30-12:00	TA1 User: Low Power Design Power Gating using UPF, DC & ICC for a PCIE Design AMD ------ Energy Harvesting w/ an ARM Cortex-M0: A Novel Application of UPF w/ Synopsys™ Galaxy Platform to Implement Sub-Clock Power Gating University of Southampton; ARM Ltd	TA2 Vision & Tutorial: Advanced Design Integration – 2.5DIC & 3DIC A Silicon Interposer-Based 2.5D-IC Design Flow - Going 3D by Evolution Rather Than by Revolution Synopsys, Inc. ------ Xilinx FPGAs w/ SSI Technology – Concept to Silicon development overview Xilinx	TA3 User: UVM RAL & Solution for X Propagation Easier RAL: All You Need to Know About the UVM Register Abstraction Layer Doulos ------ Enhanced simulation support for non-deterministic values FREESCALE ------ X-Optimism Elimination during RTL Verification FREESCALE; Synopsys, Inc.		TA5 User & Tutorial: FPGA Prototyping Slow Dancing w/ Memories - Sometimes it's Harder to Go Slow SanDisk ------ Determining Optimal FPGA System Connectivity Synopsys, Inc.	TA6 User: MultiVoltage & Low Power Analysis Technologies 28nm ETM Generation w/ Multi-voltage Domain (UPF compliant) & Embedded IO LSI ------ Early Leakage Power Estimation for Use Cases Across PVT Broadcom	TA7 User: Designing Custom Processors as an Alternative to Fixed HW Blocks Programmable Accelerator for a Mobile SoC Audience ------ Deploying Processor Designer for a Custom Super Scalar Processor for Software Defined Radio Fujitsu
12:00-1:15	General Lunch in Hall D
	Lunch and Learn in Mission City Ballroom Your Peers are Benefiting from the Latest Design Compiler Technologies, Are You?
	Lunch and Learn in Room 209/210 Managing Power Intent on Hierarchical Designs using UPF with the Lynx Design System
	IC Design - Implementation A	IC Design - Implementation B	IC Verification		FPGA	IC Design - Signoff	System-Level Design
1:15-2:45	TB1 User & Tutorial: Automated Design Planning & Design Closure Hippo Lake: A Case Study of Automated Design Planning in High Speed Designs Intel Corp. ------ Faster Top Level Closure w/ Transparent Interface Optimization (TIO) Synopsys, Inc.	TB2 Vision: Designing 100 Billion Transistor Chips Synopsys, Inc.	TB3 User: Simultaneous C/Assembly/ RTL Debug w/ DVE & SimpleTest Writer Interface w/ SystemVerilog Gate & RTL Level Simulation w/ Software Debug Capability - An Integrated Signal & C-code Debugger in DVE Broadcom Corp. ------ Mechanism to Allow Easy Writing of Test Cases in a SystemVerilog Verification Environment, Then Auto-Expand Coverage of the Test Case Verifysys		TB5 User & Tutorial: FPGA Prototyping Functional Coverage for FPGA Prototypers Opens a new Paradigm Intel Corp. ------ Effective Strategies for Bringing Up & Debugging an FPGA-Based Prototype Synopsys, Inc.	TB6 Tutorials: Parasitic Extraction for Emerging Technologies Dealing w/ Metal Fill in 28nm ECO Extraction Flow Synopsys, Inc. ------ Double-Patterning Aware Extraction & Timing Signoff at 20nm Synopsys, Inc. ------ How do FinFETs Impact Parasitic Modeling & Extraction? Synopsys, Inc.	TB7 User: Early SoC Architecture Performance Analysis System on Chip (SoC) Architecture/ Performance Modeling using SystemC/TLM 2.0, a Case Study using Platform Architect LSI ------ Architecture Analysis of a Multi-Mode Base-Station Huawei
2:45-3:15	Break
	IC Design - Implementation A	IC Design - Implementation B	IC Verification	IC Design - Test	FPGA	IC Design - Signoff	System-Level Design
3:15-5:15	TC1 Tutorial & Panel: Optimized Implementation for High Performance Cores Techniques for High Performance Cores using Synopsys Galaxy Platform - ARM® Cortex™-A15 Case Study Synopsys, Inc. ------ Ask the Experts Panel: Best Practices for High Performance Processor Core Implementation Synopsys, Inc.	TC2 User Session: Clock Tree Design Multi-Source CTS in ICC AMD ------ Gater Expansion w/ a Fixed Number of Levels to Minimize Skew AMD	TC3 Tutorial: AMBA ACE VIP & Low-Power Simulation Debug Achieving Rapid Verification Convergence w/ AMBA ACE VIP Synopsys, Inc. ------ Debugging Low-Power Simulations Synopsys, Inc.	TC4 Tutorial: Test Updates, Yield Improvement, & the Importance of Standards Synopsys, Inc.	TC5 User & Tutorial: FPGA Design Unleashing the Power of the Command-Line Interface Centellax ------ Solving P&R Challenges on High Density Xilinx FPGAs Xilinx	TC6 Tutorial: Signoff using Formal Equivalence Checking Formality Low Power Equivalence Checking w/ UPF Synopsys, Inc. ------ ESP Memory Redundancy Verification Synopsys, Inc.	TC7 Tutorial: Enabling Early Software Dev. for ARM-Based Designs Developing Software for ARM big.LITTLE Based Designs Running Android ARM; Synopsys, Inc. ------ SoC FPGA Virtual Target: An Application of Virtual Prototyping Synopsys, Inc.
4:30-7:00	SNUG Pub

Wednesday, March 28, 2012

Time	Description
7:30-9:00	Registration
9:00-10:00	Technology Keynote: Dr. Chenming Hu, Professor Emeritus, University of California, Berkeley and former TSMC CTO
10:00-10:30	Break
	IC Design - Implementation A	IC Design - Test	IC Verification	Compute & Design Infrastructure	IP Summit
10:30-12:00	WA1 User: Design Planning Powerful Things you can do w/ TemplateBased Power Network Synthesis Combined w/ Basic Polygon Operations in IC Compiler Cypress Semiconductor ------ Developing & Implementing a Flip Chip Interface using IC Compiler Samsung	WA2 User: Optimizing Test Time w/ SerDes & Mfg. Data Analysis w/ Yield Explorer Commonality Analysis w/ Yield Explorer NVIDIA ------ OptimizingTest Times using Deserializer/ Serializer Scan Architecture NVIDIA	WA3 Tutorial: VCS Technology & Testbench Methodology for Achieving Higher Video throughput Synopsys, Inc.	WA4 Tutorial: Compute Farm Infra. for EDA Optimizing Scale Out for Synopsys EDA Tools using a Common Distributed Processing Framework Synopsys, Inc. ------ Rightsizing EDA Infrastructure & Impact of Low Power Processors on EDA Synopsys, Inc.	WA5 Tutorial: Best Practices to Implement Memories & Libraries to DeliverSuperior PPA & Embedded Test & Repair Synopsys, Inc.	WA6 Tutorial: Designing to the New PCI Express 3.0 Equalization Requirement Synopsys,Inc.	WA7 Tutorial: Tag-You’re it! Passive, Unclonable RFID Tags Made Possible Verayo
12:00-1:15	General Lunch in Hall D
12:00-1:15	Lunch and Learn in Mission City Ballroom TSMC Presents: The Scaling Factor – The Impact of Process Migration on IP Design
	IC Design - Implementation A	IC Design - Test	IC Verification	Compute & Design Infrastructure	IP Summit
1:15-2:45	WB1 Tutorial: IC Compiler: Achieving Design Success at 20nm Synopsys, Inc.	WB2 User: PowerEfficient Clocking for Test &Custom Scan Chain Stitching w/ DFTC Power-Efficient Functional & Scan Clocking for High Performance Cores AMD ------ Scan Stitching Separate Groups of Mux-D or LSSD Flops AMD	WB3 Tutorial: Getting X Propagation under Control Synopsys, Inc.	WB4 Tutorial: Compute Farm Resource Usage & Optimization Business Rules Monitoring – Automated Resource Policy Implementatin Altera; Synopsys, Inc. ------ Leveraging Adaptive Resource Optimization w/ Lynx Synopsys, Inc.	WB5 Tutorial: Meeting Quality of Service Requirement w/ DDR Memory Controllers Synopsys, Inc.	WB6 Tutorial: Create a Complete Audio IP Subsystem for Your SoC in Minutes Synopsys, Inc.	WB7 Tutorial: Getting the Most from Synthesis to Improve YourDatapath QoR Synopsys, Inc.
2:45-3:30	Break & Best Paper Awards
	IC Design - Implementation A	IC Design - Test	IC Verification	Compute & Design Infrastructure	IP Summit
3:30-5:00	WC1 Tutorial: Advanced Multichip Design Design of a 2.5D Silicon Interposer using IC Compiler Synopsys, Inc. ------ Creating Multi-IO Ring Die using IC Compiler Synopsys, Inc.	WC2 Panel: Testing High-Frequency & Low-Power Designs: Do the Standard Rules Apply? Oracle; Synopsys, Inc.	WC3 Tutorial: VCS Technologies for Efficient Development & Debug of UVM Testbenches Synopsys, Inc.	WC4 Tutorial: Management of High-Performance Compute Resources Understand the Impact of NFS Overhead Synopsys, Inc. ------ HPC for Silicon Design Inside Intel Intel, Corp.	WC5 Tutorial: USB 3.0: Ready, Set, Integrate! Synopsys, Inc.	WC6 Tutorial: Future Mobile Interfaces & Integration of MIPI DigRF in Mobile Baseband Processors Synopsys, Inc.	WC7 Tutorial: The Role of IP in More Moore & More than Moore Synopsys, Inc.

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